1. Field of the Invention
The present invention relates to a static type semiconductor device, and specifically, to a static type semiconductor memory device including a memory cells each provided at crossing portion of a word line and first and second bit lines, and a dummy memory cell provided at a crossing portion of a word line and first and second dummy bit lines.
2. Description of the Background Art
Conventionally, a method of increasing the speed and reducing power dissipation of a static random access memory (hereinafter referred to as an SRAM) using a dummy memory cell has been proposed. For example, Japanese Patent Laying-Open No. 11-339476 discloses a method using a dummy memory cell. In the method, when potential of a word line corresponding to an address signal is changed to a select level, the dummy memory cell is activated simultaneously with a regular memory cell to output a prescribed read signal. According to this method, as potential of the word line is changed to a select level, the level of read signal is changed by a dummy memory cell corresponding to the word line. In response to the level change of the read signal, the word line may be lowered to a non-select level or a sense amplifier may be activated to read data signal. Accordingly, wasteful discharge of a bit line may be eliminated to attain low power dissipation, or activation timing of a sense amplifier and precharge may be optimized to attain reduction of reading cycle time.
Usually, a transistor in a memory cell is designed to be as small as possible to achieve higher integration of the memory cell. As a result, when potential of a bit line is lowered by a memory cell, the potential change occurs slowly and potential difference between the pair of bit lines will be very small. As such, a differential sense amplifier circuit of higher sensitivity is used for detecting read data signal sensing small potential difference between the pair of bit lines in order to attain high-speed read operation. According to the method of Japanese Patent Laying-Open No. 11-339476, however, since only one dummy cell is activated by the selected word line, the potential change timing of a signal line carrying read signal from the dummy cell, i.e., the dummy bit line, will be identical to that of the regular bit line. Thus, the change of dummy bit line potential will also be very small. In effect, when sensing read signal with a level sensing circuit such as an inverter, a long time period is required until the potential of dummy bit line is pulled down lower than the threshold potential of the inverter, and thus optimal timing can not be attained.
Additionally, with a single dummy memory cell being activated, margins must be maintained, considering variations in pull-down current value of the selected dummy memory cell and that of regular memory cell, i.e., the current drawn from bit lines by the memory cell and dummy memory cell. As downscaling advances and fine processing becomes practical, variations in finished shape and in injection dose of impurities, and thus in transistor characteristics, become wider. Lower voltage results in higher degree of variation. Thus, the characteristics of transistors in dummy memory cells will be varied among cells. For example, a dummy memory cell which is activated by a particular selectively driven word line may tends to have transistors with superior characteristics resulting in rapid potential change of dummy bit line, while a regular memory cell may conversely tends to have transistors with poor characteristics resulting in slow potential change of regular bit line, in which case malfunction may occur due to the premature timing of pulling down potential of word line or of activating sense amplifier. In an attempt to avoid such situation, to maintain margin for achieving stable operation even under the worst condition will only delay the sensing timing of read signal against the original intention, and thus desired high-speed and reduced power dissipation can not be attained.
One article (ISSCC 2001, xe2x80x9cUniversal-Vdd 0.65-2.0V 32 kB Cache using Voltage-Adapted Timing-Generation Scheme and a Lithographical-Symmetric Cellxe2x80x9d) describes a scheme to pull down potential of a dummy bit line by a plurality of dummy memory cells, in order to average the variation of the characteristics of transistors for advancing output timing of read signal, in consideration of the aforementioned problem. According to this article, however, since the dummy memory cells are activated by the dummy word lines, the dummy bit line is pulled down at a timing earlier than the activation timing of the regular memory cells. As such, though margin is increased by averaging pull down speed using a plurality of dummy memory cells and thus addressing the variation, difference between the rising timing of dummy word lines and that of regular word lines must be considered on designing, which disadvantageously involves redesigning of timing when the configuration of memory cell array is changed. When applying this scheme to a variety of bit/word configurations required in the system LSI and the like, timings must be optimally designed for each case, and thus enormous period of designing and developing will be needed.
Therefore, the main object of the present invention is to provide a static type semiconductor memory device capable of optimizing operational timing with increased operational margin.
A static type semiconductor memory device of the present invention includes a memory cell arranged at crossing portion of a word line and first and second bit lines, and a dummy memory cell arranged at crossing portion of the word line and first and second dummy bit lines. The memory cell includes two P-channel MOS transistors for loading, two N-channel MOS transistors for driving, and two N-channel MOS transistors for accessing, and in response to corresponding word line being changed to select level, lowers potential of one of the first and second bit lines precharged at power supply potential to ground potential via one N-channel MOS transistor for accessing and one N-channel MOS transistor for driving. The dummy cell includes first and second N-channel MOS transistors provided corresponding to two P-channel MOS transistors for loading, third and fourth N-channel MOS transistors provided corresponding to two N-channel MOS transistors for driving, and fifth and sixth N-channel MOS transistors for accessing, and in response to the word line being changed to select level, lowers potential of the first dummy bit line, of the first and second dummy bit lines precharged to the power supply potential, to the ground potential via the fifth N-channel MOS transistor and at least two of the first to fourth N-channel MOS transistors connected in parallel. Accordingly, since potential of first dummy bit line decreases more quickly than that of the first or the second bit line, timing for changing word line to non-select line and the like can easily be optimized. Additionally, since potential of the first dummy bit line is lowered by the fifth N-channel MOS transistor for accessing and two N-channel MOS transistor connected in parallel, even when the characteristics of the first to the sixth N-channel MOS transistors in the dummy memory cell vary, degree of the variation can be averaged to be smaller, and hence increased operational margins can be attained.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.